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JA58560
Mask-ROM 8-Bit CMOS Micro-controller
Features
Total of 33 single word instructions The fast execution time may be 200ns for all single cycle instructions under 20MHz operation Operating voltage range: RC: 2.4V ~ 6.0V XTAL: 2.4 V ~ 6.0V LFXTAL: 2.4V ~ 6.0V HFXTAL: 3.0V ~ 6.0V 8-bit data bus 14-bit instruction word Four-level stacks On chip ROM size: 1Kx14 bits for JA58560 Internal RAM size: 25 bytes for JA58560 Direct and indirect addressing modes for data accessing 8-bit real time clock/counter with 8-bit programmable prescalers Internal power-on Reset Device Reset Timer Code protection Sleep mode for power saving On chip Watchdog Timer (WDT) based on internal RC oscillator Three I/O ports PA, PB and with independent direction control 4 types of oscillators can be selected by code options: RC : Low-cost RC oscillator XTAL : Standard crystal oscillator HFXTAL : High frequency crystal oscillator
LFXTAL : Low frequency crystal oscillator
General Description
JA58560 series is an ROM based 8-bit microcontroller which employs a full CMOS technology enhanced with low cost, high speed and high noise immunity. Watchdog Timer, RAM, ROM, tri-state I/O port, power down mode, and real time programmable clock / counter are integrated into this chip. JA58560 contains 33 instructions, all are single cycle except for program branches which take two cycles. On chip memory is available with for 1Kx14 bits of ROM for JA58560 and 25 bytes of static RAM.
Block Diagram
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Pin Assignment
Pad Assignment
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Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 Pad Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VDD X 115.75 235.75 355.75 475.75 595.75 715.75 835.75 955.75 1075.75 Y 143 143 143 143 143 143 143 143 143 Pad No. 10 11 12 13 14 15 16 17 18 Pad Name OSCO OSCI PA0 PA1 PA2 PA3/SDA TOCKI/SCL MCLR/VPP VSS X 1030.5 910.5 790.5 670.5 550.5 430.5 310.5 190.5 75.5 Y 1380 1380 1380 1380 1380 1380 1380 1380 1380
Chip size : 1151.05 x 1523.05 m2
Pin Descriptions
Pad Name OSCI I/O I O OSCO T0CKI/SCL MCLR PA0~PA3 PB0~PB7 VDD VSS I I I/O I/O Description RC type: Input pin of RC oscillator Crystal type: Input terminal of crystal oscillator RC type: OSCO outputs with 1/4 frequency of OSCI to denote the cycle rate for instruction. Crystal type: Output terminal of crystal oscillator Input pin of real time counter/clock. Must be tied to Vss or Vdd when unused. Input pin for device reset. PA0~PA3 as bi-directional I/O port PB0~PB7 as bi-directional I/O port Power supply Ground Ta = 0 to 70 GND=0V to +70 to +150
Absolute Maximum Rating
Ambient Operating Temperature ....................................................................................................0 Store Temperature .................................................................................................................... -65
DC Supply Voltage (VDD) ..................................................................................................................... 0V to +6V Voltage with respect to Ground (VSS).....................................................................................0.6V to (VDD+0.6V)
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Operating Conditions
Ta = 0 to 70 GND=0V to 70
DC Supply Voltage....................................................................................................................... +2.4V to +6.0v Operating Temperature.....................................................................................................................0
Electrical Characteristics (Under Operating Conditions)
Electrical characteristics of JA58560 Parameter Input High Voltage Symbol VIH Condition I/O port, when VDD=5V MCLR, when VDD=5V I/O ports, when VDD=5V MCLR, when VDD=5V I/O ports, VDD=4.5V, IOH=-5.4mA, IOL=8.7mA ; in RC mode IOL=10mA 3.6 0.6 Min. 2.0 3.7 1.2 1.5 Typ. Max. Unit V V V V V V
Input Low Voltage
VIL VOH VOL
Output Voltage
HFXTAL: 20MHz, WDT disable, COSCI=27pF, COSCO=20pF VDD=6.0V IDD VDD=5.0V VDD=4.0V VDD=3.0V 3.135 2.365 1.574 1.014 mA mA mA mA
HFXTAL: 12MHz, WDT disable, COSCI=27pF, COSCO=20pF VDD=6.0V VDD=5.0V Operating Current IDD VDD=4.0V VDD=3.0V VDD=2.4V 2.111 1.497 1.040 0.629 0.451 mA mA mA mA mA
XTAL: 12MHz, WDT disable, COSCI=27pF, COSCO=20pF VDD=6.0V VDD=5.0V IDD VDD=4.0V VDD=3.0V VDD=2.4V 2.423 1.697 1.154 0.697 0.476 mA mA mA mA mA
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Parameter Symbol Condition Min. Typ. Max. Unit
XTAL: 4MHz, WDT disable, COSCI=27pF, COSCO=20pF VDD=6.0V VDD=5.0V IDD VDD=4.0V VDD=3.0V VDD=2.4V 1.332 0.955 0.613 0.358 0.235 mA mA mA mA mA
LFXTAL: 32kHz, WDT disable, COSCI=27pF, COSCO=20pF VDD=6.0V VDD=5.0V IDD VDD=4.0V VDD=3.0V VDD=2.4V 43.14 22.45 10.28 5.338 3.355 A A A A A
VDD=5V, RC mode, WDT Disable. These values include current though Text R=1k Operating Current R=2k R=3.3k R=4.7k IDD C=3P R=5.1k R=10k R=47k R=100k R=300k R=1k R=2k IDD C=20P R=3.3k R=4.7k R=5.1k R=10k F=14.31MHz F=12.5MHz F=9.883MHz F=8.191MHz F=7.847MHz F=4.763MHz F=1.300MHz F=640.7kHz F=216kHz F=11.54MHz F=8.32MHz F=5.974MHz F=4.605MHz F=4.352MHz F=2.394MHz 4.56 2.873 1.885 1.448 1.376 0.769 146.8 105.2 43.1 4.295 2.43 1.504 1.096 1.029 0.543 mA mA mA mA mA mA A A A mA mA mA mA mA mA
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Parameter Symbol Condition R=47k IDD C=20P R=100k R=300k R=1k R=2k R=3.3k R=4.7k IDD C=100P R=5.1k R=10k R=47k Operating Current R=100k R=300k R=1k R=2k R=3.3k R=4.7k IDD C=300P R=5.1k R=10k R=47k R=100k R=300k F=591.3kHz F=283.8kHz F=95.97kHz F=5.433MHz F=3.329MHz F=2.168MHz F=1.583MHz F=1.482MHz F=756.8kHz F=173.6kHz F=82.72kHz F=27.68kHz F=2.535MHz F=1.459MHz F=915.1kHz F=655.4kHz F=611.6kHz F=306.9kHz F=68.81kHz F=32.62kHz F=10.86kHz Min. Typ. 132.8 69.76 29.64 3.53 1.799 1.112 0.796 0.746 0.38 90.72 47.98 21.48 3.1 1.567 0.957 0.681 0.636 0.32 76.78 41.13 19.21 Max. Unit A A A mA mA mA mA mA mA A A A mA mA mA mA mA mA A A A
WDT Disable, COSCI=27pF, COSCO=20pF VDD=6.0V VDD=5.0V Sleeping Current IDD VDD=4.0V VDD=3.0V VDD=2.4V 1.378 1.004 0.725 0.499 0.375 uA uA uA uA uA
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The registers of JA58560 The registers of JA58560 Address 00H 01H 02H 03H 04H 05H 06H 07H~1FH Description Indirect addressing register Timer0 PC Status FSR Port A Port B General purpose register
INAR (Indirect Address Register) : 00H INAR is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction accessing this register can access data pointed by FSR(04H). Timer0 (8-bit real-time clock/timer) : 01H This register increases by an external signal edge applied to T0CKI pin, or by internal instruction cycle. It can be read or written as any other register. PC (Program Counter) : 02H This register increases itself along with every instruction cycle, except the following condition specified in Figure 3.1:
LCALL, LGOTO: from instruction word RETIA: from STACK
LCALL A10~A0 RETIA Stack 1 Stack 2 Stack 3 Stack 4
Program Counter
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Status (Status Register) : 03H The content of Status register is listed in Table. Bit Symbol Description
0
C
Carry/borrow bit ADDAR = 1, a carry occurred = 0, a carry did not occur SUBAR = 1, a borrow did not occur = 0, a borrow occurred Half carry/half borrow bit ADDAR = 1, a carry from the 4th low order bit of the result occurred = 0, a carry from the 4th low order bit of the result did not occur SUBAR = 1, a borrow from the 4th low order bit of the result did not occur = 0, a borrow from the 4th low order bit of the result occurred Zero bit = 1, the result of a logic operation is zero = 0, the result of a logic operation is not zero
1
DC
2
Z
3
PD
Power down flag bit: = 1, after power-up or by the CLRWDT instruction = 0, by the SLEEP instruction Time overflow flag bit: = 1, after power-up or by the CLRWDT or SLEEP instruction = 0, a WDT time-overflow occurred Reserved
4 5~7
TO -
FSR (File select register pointer): 04H Bit 0~4 are used to select up to 32 registers (address: 00h~1Fh). In JA58560, Bit 5~7 were fixed 1. The indirect addressing mode shows as below:
Data Memory Configuration
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PORT A: 05H PA3:PA0, bi-directional I/O Register PORT B: 06H PB7:PB0, bi-directional I/O Register T0MODE REGISTER: T0MODE is a write-only register and the content is listed in Table. Bit Symbol Description Bit Value 000 001 010 011 100 101 110 111 Prescaler assign bit: = 0, Timer0 = 1, WDT Timer0 source signal edge select bit: = 0, increment when low-to-high transition on T0CKI pin = 1, increment when high-to-low transition on T0CKI pin Timer0 source signal select bit: = 0, internal instruction clock cycle = 1, transition on T0CKI pin Reserved Timer Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Ratev 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
2~0
PS0:PS0
3
PSC
4
TE
5 6~7
TS -
IOST (Control Port I/O Mode Register) The IOST register is "write-only" = 0, I/O pin in output mode; = 1, I/O pin in input mode. I/O Ports Equivalent Circuit
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Note: 1. The IOST registers are "write-only" and set upon RESET. 2. If the IOST latch is "0", the corresponding I/O pin is in output mode; if the IOST latch is "1", the corresponding I/O pin is in input mode. RESET This device may be reset by one of the following ways: (1) Power-on Reset: At power-up, this device is kept in a RESET condition for a period of 18ms after the voltage on MCLR pin has reached a logic high level. (2) MCLR reset (normal operation). (3) WDT reset (normal operation). (4) MCLR wake-up (from sleep mode). (5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device to enter sleep mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This device can be awakened by WDT time-out or reset input on MCLR pin. The contents of registers after reset are listed below: Address Register Power-On Reset 00h 01h 02h 03h 04h 05h 06h 07h-1Fh N/A N/A N/A Note: x = unknown, u = unchanged, - = unimplemented, read as 0 , # = refer to the following table Condition MCLR Reset (not during SLEEP) MCLR Reset during SLEEP WDT Reset (not during SLEEP) WDT Reset during SLEEP Status: bit 4 u 1 0 0 Status: bit 3 u 0 1 0 INAR Timer0 PC STATUS FSR PORTA PORTB General Purpose Register Acc IOST T0MODE xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 111x xxxx ---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 --11 1111 MCLR or WDT Reset uuuu uuuu uuuu uuuu 1111 1111 000# #uuu 111u uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 --11 1111
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Real Time Clock (Timer0) and Watchdog Timer
T0CKI TE
WDT Enable
1 0 M U X
WDT
1 0
fOSC/4
1
0
TS
PSC
MUX
PSC
MUX
Sync 2 Cycles
8-Bit prescaler
8 Bits
Timer 0 8 Bits Data Bus
PS2:PS0
8-to-1 MUX
1 PSC MUX
0
WDT Time-out
Timer0 Timer0 is an 8-bit timer/counter. The clock source of Timer0 may come from the internal clock or by an external clock source presented at the T0CKI pin. To select the internal clock source, bit 5 of the T0MODE register should be clear. In this mode, Timer0 increases 1 on every instruction cycle (without prescaler). To select the external clock source, bit 5 of the T0MODE register should be set. In this mode, Timer0 increases 1 on every falling or rising edge of T0CKI pin, which was be controlled by bit 4 of T0MODE register. Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator. This RC oscillator is separated from the RC oscillator of the OSCI pin. That means the WDT keeps running even when the oscillator driver is turned off, such as in sleep mode. During normal operation or in sleep mode, a WDT time-out causes the device reset and the TO bit (bit 4 of STATUS register) is cleared. Without prescaler, the WDT time-out period is 18ms. This period can be increase by using the prescaler. The division ratio of prescaler is up to 1:128. Thus, the longest time-out period is approximately 2.3s. Prescaler The 8-bit prescaler may be assigned to either the Timer0 or the WDT through the PSC bit (bit 3 of the T0MODE register). Setting this bit assigns the prescaler to the WDT. Resetting this bit assigns the prescaler to the Timer0. The PS2:PS0 bits determine the prescale ratio. The prescaler can not be assigned to both the Timer0 and WDT simultaneously.
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Oscillator Configuration This device supports four oscillator modes. Users can program two configuration bits to select the appropriate mode. These oscillator modes offered as: RC: Low-cost oscillator XTAL: Standard crystal oscillator HFXTAL: High frequency crystal oscillator LFXTAL: Low frequency crystal oscillator XTAL, HFXTAL or LFXTAL modes
RC Oscillator Mode
R OSCI C 4 OSCO
JA58560
Internal clock
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Instruction Table
Mnemonic Operands BCR R, bit BSR R, bit BTRSC R, bit BTRSS R, bit CLRWDT T0MODE SLEEP IOST R ANDIA I XORIA I MOVIA I IORIA I RETIA I LCALL I LGOTO I NOP MOVAR R COMR R, d MOVR R, d RRR R, d RLR R, d SWAPR R, d CLRA CLRR R INCR R, d INCRSZ R, d DECR R, d Clear bit in R Set bit in R Test bit in R and skip if clear Test bit in R and skip if set Clear Watchdog Timer Load T0MODE Register Go into standby mode Load IOST Register AND immediate with Acc Exclusive OR immediate with Acc Move immediate to Acc Inclusive OR immediate with Acc Return, place immediate in A Call subroutine Unconditional branch No operation Move Acc to R Complement R Move R Rotate right R Rotate left R Swap halves R Clear Acc Clear R Increment R Increment R, Skip if 0 Decrement R Description Cycles 1 1 1 or 2(skip) 1 or 2(skip) 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 or 2(skip) 1 Instruction Code 11 11bb brrr rrrr 11 10bb brrr rrrr 11 01bb brrr rrrr 11 00bb brrr rrrr 01 0000 0000 0001 01 0000 0000 0010 01 0000 0000 0011 01 0000 0000 0rrr 00 1001 iiii iiii 00 1000 iiii iiii 00 0001 iiii iiii 00 0011 iiii iiii 00 1100 iiii iiii 10 0iii iiii iiii 10 1iii iiii iiii 01 0000 0000 0000 01 0000 1rrr rrrr 01 0010 drrr rrrr 01 0011 drrr rrrr 01 1110 drrr rrrr 01 1100 drrr rrrr 01 1101 drrr rrrr 01 0001 0000 0000 01 0001 1rrr rrrr 01 1000 drrr rrrr 01 100 1 drrr rrrr 01 0110 drrr rrrr Status Affected None None None None TO, PD None TO, PD None Z Z None Z None None None None None Z Z C C None Z Z Z None Z
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Mnemonic Operands Description Cycles 1 or 2(skip) 1 1 1 1 1 Instruction Code 01 0111 drrr rrrr 01 1010 drrr rrrr 01 1011 drrr rrrr 01 0100 drrr rrrr 01 0101 drrr rrrr 01 1111 drrr rrrr Status Affected None C, DC, Z Z Z C, DC, Z Z
DECRSZ R, d Decrement R, Skip if 0 SUBAR R, d XORAR R, d ANDAR R, d ADDAR R, d IORAR R, d Note: b i : Bit position : Immediate data Subtract Acc from R Exclusive OR Acc with R AND Acc with R Add Acc and R Inclusive OR Acc with R
WDT : Watchdog Timer Acc TO C R : Accumulator : Time overflow bit : Carry flag : (r6 r5 r4 r3 r2 r1 r0)
R
: Register address
T0MODE : T0MODE register IOST DC : I/O port status register : Digital carry flag
PD : Power down flag Z I D : Zero flag : (i7 i6 i5 i4 i3 i2 i1 i0) [0,1]
Destination: If d is "0", the result is stored in the Acc register. If d is "1", the result is stored back in register R.
Order Information
Type 18pins 300mil PDIP JA58560N 600mil PDIP 300mil SOP JA58560P Die Form JA58560
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Package Dimension
18 Pin PDIP 300mil for JA58560N
D
15 4x)
E1
E
eB
0.727
Top E-Pin Indent Bottom E-Pin Indent 0.118
0.079
C
A L e B1 B D1
A2
A1
Symbol Min A A1 A2 B B1 C D D1 e E1 E L eB 3.18 8.38 0.36 1.27 0.20 0.13
Dimension in Millimeters Nom Max 4.57 Min
Dimension in Millimeters Nom Max 0.180 0.005
0.30 0.46 1.52 0.25 22.96 0.56
3.56 0.56 1.78 0.33 23.11 0.69 8.26 0.014 0.050 0.008 0.894 0.017 0.300 0.252
0.140 0.022 0.070 0.013 0.910 0.027 0.325 0.262
22.71 0.43 7.62 6.40
6.50 2.54
6.65
0.125 9.65 0.330 0.380
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18 Pin SOP for JA58560P
7 4x)
E
H 0.020 x 45
view "A"
C D 7 4x) A2 e B A1 L A view "A"
Symbol Min A A1 A2 B C D E e H L 0.33 0.18 2.36 0.10
Dimension in Millimeters Nom 2.49 Max 2.64 0.30 2.31 0.41 0.23 0.51 0.28 11.76 7.49 1.27 10.01 0.38 0 10.31 0.81 10.64 1.27 8 7.59 Min
Dimension in Millimeters Nom 0.098 Max 0.104 0.012 0.091 0.013 0.007 0.447 0.291 0.295 0.050 0.394 0.015 0 0.406 0.032 0.419 0.050 8 0.016 0.009 0.020 0.011 0.463 0.299
0.093 0.04
11.35 7.39
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